`timescale 1ns/1ps
`default_nettype none
//文件名: rtl/alu.v
//作用：运算单元
module alu(
    input  wire [31:0] a,
    input  wire [31:0] b,
    input  wire [3:0]  alu_ctrl,  
    output reg  [31:0] y
);

    wire [4:0] shamt = b[4:0];
    wire signed [31:0] a_s = a;
    wire signed [31:0] b_s = b;

    always @* begin
        case (alu_ctrl)
            4'b0000: y = a + b; // ADD / ADDI
            4'b0001: y = a - b;   // SUB
            4'b0010: y = a << shamt;                   // SLL / SLLI
            4'b0011: y = (a_s < b_s) ? 32'd1 : 32'd0;  // SLT / SLTI
            4'b0100: y = (a   < b  ) ? 32'd1 : 32'd0;  // SLTU/ SLTIU
            4'b0101: y = a ^ b;                        // XOR / XORI
            4'b0110: y = a >> shamt;                   // SRL / SRLI
            4'b0111: y = a_s >>> shamt;                // SRA / SRAI
            4'b1000: y = a | b;                        // OR  / ORI
            4'b1001: y = a & b;                        // AND / ANDI
            default: y = 32'b0;
        endcase
    end
endmodule

